In manufacturing a semiconductor device, metal wirings are used to electrically connect devices or wirings to each other.
Although aluminum Al or tungsten W may be used as materials for metal wiring, they have a low melting point and high resistivity. Accordingly, it is difficult to apply aluminum Al or tungsten W to a highly integrated semiconductor device. As the degree of integration in semiconductor devices escalates, a demand for a material having low resistivity and excellent reliability including high electro-migration (referred to as ‘EM’) and stress-migration (referred to as ‘SM’). Recently, copper has been considered the most suitable material to meet the demand.
However, wiring processes using copper have problems with etching and increased corrosion. It is very difficult to substitute copper into the type of wiring processes used on aluminum and tungsten.
To overcome this, a single damascene or dual damascene process may be applied. In particular, the dual damascene process has found favor. A via first dual damascene (referred to as ‘VFDD’ hereinafter), a trench first dual damascene (referred to as ‘TFDD’ hereinafter), and a self-align dual damascene (referred to as ‘SADD’ hereinafter) are alternatives of dual damascene processes.
FIGS. 1A through 1E are views illustrating a method for manufacturing a semiconductor device with a dual damascene pattern according to the related art. As shown in FIG. 1A, a first interlayer dielectric 30 is formed over a substrate 10 on which a lower metal wiring 20 is formed. Next, a capping layer 40 is formed over the first interlayer dielectric 30 including the lower metal wiring 20, and a second interlayer dielectric 50 is formed over the capping layer 40.
As shown in FIG. 1A, a via hole pattern is formed and etched on the second interlayer dielectric 50 using a photoresist layer (not shown) to form a via hole H1. An ashing process, using plasma generated by RF or microwaves, removes the photoresist material forming the via hole pattern.
As shown in FIG. 1B, the via hole H1 is filled with a first photoresist layer 60. As shown in FIG. 1C, photoresist layer 60 is removed, except the photoresist inside the via hole H1. The remaining photoresist will be used during a subsequent process as an etch barrier.
As shown in FIG. 1D, a second photoresist layer 70 is deposited, exposed, and developed over the second interlayer dielectric 50, to form a trench pattern T1.
However, a reaction between the second interlayer dielectric 50 and the first photoresist layer 60 causes photoresist poisoning. Photoresist poisoning causes an upper portion of the first photoresist layer 60 to become swollen.
Photoresist poisoning indicate that components of an upper portion of the first photoresist layer 60 react with components in the second interlayer dielectric 50, which has a low dielectric constant, as shown with A of FIG. 1D.
A trench is formed by using the second photoresist layer 70 as an etch mask and the first photoresist layer 60 as an etch stop layer.
Then, as shown in FIG. 1E, the first photoresist layer 60 is removed by ashing. After the capping layer 40 is etched to expose metal wiring 20, the via hole and trench are filled with copper to simultaneously form a via plug 80 and a lower metal wiring 90.
However, as shown in FIG. 1E, the poisoning A of the first photoresist causes the etch of the second interlayer dielectric 50 to leave behind a residual part A′. This causes a shape of the lower metal wiring 90 to be distorted, resulting in increased resistance of the metal wiring.
Moreover, the etching and ashing processes use high intensity plasma during various stages of the metal wiring process. When high intensity plasma is used, a strong electric field between the gate and substrate of the semiconductor device can cause plasma damage to the gate insulating layer. This may be characterized as significant charge damage.
The damage in the gate insulating layer may change the threshold voltage, reduce the duration of a conductance of a gate insulating layer, or damp a drain current, all of which result in degraded operation of the semiconductor device.
In addition, the plasma damage occurs during a plasma etching process for forming trenches, an ashing process for removing a photoresist layer, and a plasma etching process for removing a via etch stop layer.